这里涉及到一个很重要的寄存器，时钟配置寄存器：RCC_CFGR

#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
/* #define SYSCLK_FREQ_HSE HSE_VALUE */
#define SYSCLK_FREQ_24MHz 24000000
#else
/* #define SYSCLK_FREQ_HSE HSE_VALUE */
/* #define SYSCLK_FREQ_24MHz 24000000 */
/* #define SYSCLK_FREQ_36MHz 36000000 */
/* #define SYSCLK_FREQ_48MHz 48000000 */
/* #define SYSCLK_FREQ_56MHz 56000000 */
#define SYSCLK_FREQ_72MHz 72000000
#endif

/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemCoreClock variable.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;

/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#ifndef STM32F10X_CL
RCC->CFGR &= (uint32_t)0xF8FF0000;
#else
RCC->CFGR &= (uint32_t)0xF0FF0000;
#endif /* STM32F10X_CL */

/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;

/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;

/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (uint32_t)0xFF80FFFF;

#ifdef STM32F10X_CL
/* Reset PLL2ON and PLL3ON bits */
RCC->CR &= (uint32_t)0xEBFFFFFF;

/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x00FF0000;

/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000;
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;

/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000;
#else
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
#endif /* STM32F10X_CL */

#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
#endif

/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
/* Configure the Flash Latency cycles and enable prefetch buffer */
SetSysClock();

#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif
}

/**
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
* @param None
* @retval None
*/
static void SetSysClock(void)
{
#ifdef SYSCLK_FREQ_HSE
SetSysClockToHSE();
#elif defined SYSCLK_FREQ_24MHz
SetSysClockTo24();
#elif defined SYSCLK_FREQ_36MHz
SetSysClockTo36();
#elif defined SYSCLK_FREQ_48MHz
SetSysClockTo48();
#elif defined SYSCLK_FREQ_56MHz
SetSysClockTo56();
#elif defined SYSCLK_FREQ_72MHz
SetSysClockTo72();
#endif

设置RCC_CFGR寄存器的位参数，使其与外部晶振匹配得到72M系统时钟。

/**
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
* and PCLK1 prescalers.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
static void SetSysClockTo72(void)
{
__IO uint32_t StartUpCounter = , HSEStatus = ;

/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);

/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == ) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}

if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;

 /\* Flash 2 wait state \*/  
 FLASH->ACR &= (uint32\_t)((uint32\_t)~FLASH\_ACR\_LATENCY);  
 FLASH->ACR |= (uint32\_t)FLASH\_ACR\_LATENCY\_2;    

 /\* HCLK = SYSCLK \*/  
 RCC->CFGR |= (uint32\_t)RCC\_CFGR\_HPRE\_DIV1;//**AHB一分频**   
 /\* PCLK2 = HCLK \*/  
 RCC->CFGR |= (uint32\_t)RCC\_CFGR\_PPRE2\_DIV1;

 /\* PCLK1 = HCLK \*/  
 RCC->CFGR |= (uint32\_t)RCC\_CFGR\_PPRE1\_DIV2;

#ifdef STM32F10X_CL
/* Configure PLLs ------------------------------------------------------*/
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */

 RCC->CFGR2 &= (uint32\_t)~(RCC\_CFGR2\_PREDIV2 | RCC\_CFGR2\_PLL2MUL |  
                           RCC\_CFGR2\_PREDIV1 | RCC\_CFGR2\_PREDIV1SRC);  
 RCC->CFGR2 |= (uint32\_t)(RCC\_CFGR2\_PREDIV2\_DIV5 | RCC\_CFGR2\_PLL2MUL8 |  
                          RCC\_CFGR2\_PREDIV1SRC\_PLL2 | RCC\_CFGR2\_PREDIV1\_DIV5);

 /\* Enable PLL2 \*/  
 RCC->CR |= RCC\_CR\_PLL2ON;  
 /\* Wait till PLL2 is ready \*/  
 while((RCC->CR & RCC\_CR\_PLL2RDY) == )  
 {  
 }

 /\* PLL configuration: PLLCLK = PREDIV1 \* 9 = 72 MHz \*/  
 RCC->CFGR &= (uint32\_t)~(RCC\_CFGR\_PLLXTPRE | RCC\_CFGR\_PLLSRC | RCC\_CFGR\_PLLMULL);  
 RCC->CFGR |= (uint32\_t)(RCC\_CFGR\_PLLXTPRE\_PREDIV1 | RCC\_CFGR\_PLLSRC\_PREDIV1 |  
                         RCC\_CFGR\_PLLMULL9);  

#else
/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
#endif /* STM32F10X_CL */

 /\* Enable PLL \*/  
 RCC->CR |= RCC\_CR\_PLLON;

 /\* Wait till PLL is ready \*/  
 while((RCC->CR & RCC\_CR\_PLLRDY) == )  
 {  
 }

 /\* Select PLL as system clock source \*/  
 RCC->CFGR &= (uint32\_t)((uint32\_t)~(RCC\_CFGR\_SW));  
 RCC->CFGR |= (uint32\_t)RCC\_CFGR\_SW\_PLL;    

 /\* Wait till PLL is used as system clock source \*/  
 while ((RCC->CFGR & (uint32\_t)RCC\_CFGR\_SWS) != (uint32\_t)0x08)  
 {  
 }  

}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}