PCIe一般规则：

purely平台

Intel UPI, Processor DMI3 (Rx lanes only), and Processor PCIe3 (Rx lanes only)
Note: PCH PCIe root port, DMI3 Rx and PCIe uplink Rx lanes are not constrained by this guideline.

目的：Length match with in a bundle in order to most effectively use a shared equalization register for that bundle.