CLOCK_DEDICATED_ROUTE=FALSE
is a placement/routing thing.

Whenever you are trying to reach a dedicated clock resource (BUFIO, BUFR, BUFMR, BUFG, BUFH, MMCM, PLL) from a pin that is a non-clock capable I/O you will get an error. This is because there are dedicated, pre-routed nets from CCIO to these resources. If you aren’t using a CCIO, then the pin has to go through general fabric routing to get to the the clock resource. Since this route is not dedicated, the latency of the insertion of this signal will vary from route to route (and isn’t easy to control). This will (generally) mess up any I/O timing associated with the clock, which is why the tools declare it as an error. You can demote the error to a warning, but you are effectively saying “I know that I won’t be able to use this clock for a high frequency I/O interface - please route it anyway”.

However, if you try to use this clock for a high performance I/O interface, it likely won’t work. The way you will know if it works or not is through proper timing constraints on the I/O. In the example of the SPI interface, if you hace accurate set_input_delay and set_output_delay commands on the SPI data pins, the tools will tell you if the interface meets or fail timing, given that the clock will have an route dependent, long, and process/voltage/temperature (PVT) varying clock insertion. For low speed I/O, you may be able to get this to work. For higher speed I/O (with smaller margins), this will fail. Furthermore, the passing/failing of this I/O interface may vary from route to route.

You are correct, Vivado defaults to using a BUFG when you place the create_clock constraint on a clock-capable FPGA input. You can force use of a BUFR instead of a BUFG by instantiating the BUFR in your project (as shown on pg206 in ug953) and connecting it to your clock-capable input, CLK_I. However, be aware that the BUFR can send the clock only to the clock-region that contains the CLK_I input. If you want to send the clock to other clock-regions of the FPGA then you will need to route it through a BUFG as shown on pg181 of ug953.

The MMCM is the most-used way to create clocks for your Vivado HDL project. It is most-used for the following reasons:
It is easy to setup (using the Clocking Wizard)
It is easy to instantiate into your project (using the instantiation template provided by the Clocking Wizard)
Constraints associated with the MMCM-created clocks are automatically written for you
It provides delay compensation.
The last of these reasons is the most important because it keeps your project clock(s) stable even as the temperature and voltage of the FPGA change.

Simply bringing CLK_I into the FPGA thru a BUFG (as you did) creates a project clock that is NOT delay compensated - and may cause your project to fail timing analysis (when it might otherwise pass timing analysis with a MMCM-created clock).

Next, I suggest that you read Xilinx document, PG065, about the Xilinx IP called the Clocking Wizard. With the Clocking Wizard you will setup a clock module called an MMCM that accepts CLK_I as an input and generates an output clock (let’s call it CLK_O) that you can send to your project.
When you create the MMCM, all the associated constraints will be automatically written for you. These automatically written constraints will not be placed in the constraints file that you have shown us. Instead, they will be placed in other .xdc files that are automatically maintained (ie. you don’t have to worry about them).

Special pathways called the “clock-tree” are used to distribute clocks throughout the FPGA. Entries and exits from the clock tree are limited. Normally, clocks can legally exit the clock-tree only to the clock-pin of a component (eg. a flip-flop). Clocks enter the clock-tree via special buffers (eg. BUFG) and special components (eg. MMCM – which uses BUFG). So, if you tried to connect a clock to the data-pin of a flip-flop then this would be an illegal exit from the clock tree and you cannot say that “you have created a clock on that pin (the data-pin)”.

BUFG/BUFGCTRL/BUFGMUX 可用于驱动全局时钟，使该时钟可以到达整个器件的逻辑。您只能通过 CCIO（具有时钟功能的 IO）引脚访问 BUFG 缓冲器。如果您需要了解有关如何使用 BUFG 缓冲器的更多详情，敬请参见 7 系列 FPGA 时钟资源用户指南 (UG472) 的“全局时钟资源”部分： http://china.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

External user clocks must be brought into the FPGA on differential clock pin pairs called clock-capable (CC) inputs. Clock-capable inputs provide dedicated, high-speed access to the internal global and regional clock resources. Clock-capable inputs use dedicated routing and must be used for clock inputs to guarantee timing of various clocking features.
General-purpose I/O with local interconnects should not be used for clock signals. Each I/O bank is located in a single clock region and includes 50 I/O pins. Of the 50 I/O pins in each I/O bank in every I/O column, there are four clock-capable input pin pairs (a total of eight pins). Each clock-capable input:
• Can be connected to a differential or single-ended clock on the PCB
• Can be configured for any I/O standard, including differential I/O standards
• Has a P-side (master), and an N-side (slave)
Single-ended clock inputs must be assigned to the P (master) side of the clock-capable input pin pair
If a single-ended clock is connected to the P-side of a differential clock pin pair, the N-side cannot be used as another single-ended clock pin—it can only be used as a user I/O. For pin naming conventions, refer to UG475, 7 Series FPGA Packaging and Pinout Specification.
Clock-capable inputs are organized as 2 MRCC and 2 SRCC pairs in each I/O bank. SRCCs access a single clock region and the global clock tree, as well as other CMTs above and below in the same column. SRCCs can drive:
• Regional clocks lines (BUFR, BUFH, BUFIO) within the same clock region
• CMTs in the same clock region and adjacent clock regions.
• Global clocks lines (BUFG) in the same top/bottom half of the device. Refer to 7 Series FPGA Packaging and Pinout Specification for BUFG and I/O bank alignments.
MRCCs can access multiple clock regions and the global clock tree. MRCCs function the same as SRCCs and can additionally drive multi-clock region buffers (BUFMR) to access up to three clock regions.
Clock-capable inputs can be used as regular I/O if not used as clocks. When used as regular I/O, clock-capable input pins can be configured as any single-ended or differential I/O standard.
Clock-capable inputs can connect to the CMT in the same clock region, and the CMT in the clock regions above and below with some restrictions.
If the dedicated routes to the other clock regions are not available, setting CLOCK_DEDICATED_ROUTE to FALSE allows the local interconnect logic to be used, although it results in longer, uncompensated delays.

The placement rules shown in Table 2-1 should be followed to ensure that the
clock-capable input pin selection has access to the desired internal clock network. Each I/O bank resides in a single clock region.

(1)I/Os and/or sequential elements throughout the device:
Clock-capable input(SRCC or MRCC) > BUFG > global clock tree
(2)I/O and/or sequential elements within a single clock region using BUFH:
Clock-capable input(SRCC or MRCC) > BUFH > horizontal clock line
(3)I/Os and/or sequential elements using CMTs:
if Throughout the device:
Clock-capable input(SRCC or MRCC) > CMT > BUFG > global clock tree
if In a single clock region or adjacent clock regions:
Clock-capable input(SRCC or MRCC) > CMT > BUFR/BUFH > regional clock tree/horizontal clock line
(4)I/Os and/or sequential elements in a single clock region using BUFR:
Clock-capable input (SRCC or MRCC)> BUFR > regional clock tree
(5)I/Os and/or sequential elements in up to three adjacent clock regions:
Clock-capable input(MRCC only) > BUFMR > BUFR > regional clock tree
(6)Only high-performance SelectIO interfaces in one clock region(50 I/Os):
Clock-capable input(SRCC or MRCC) > BUFIO > I/O clock tree
(7)Only high-performance SelectIO interfaces in up to two adjacent clock regions:
Clock-capable input(MRCC only) > BUFMR >BUFIOs > I/O clock tree

External user clocks must be brought into the FPGA on differential clock pin pairs called clock-capable inputs in order to guarantee timing of the various clocking structures described above. For more information and pin placement rules, see the section called ‘Clock-Capable Inputs’ in the 7 Series FPGAs Clocking Resources Users Guide (UG472):http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf